A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion

In this article, we present a low-power digital phase-locked loop (PLL)-based phase modulator targeting low error vector magnitude (EVM). We introduce new non-uniform clock compensation (NUCC) scheme to tackle an EVM degradation resulting from the beneficial use of time-varying sampling that is re-timed phase-modulated carrier. also employ phase-domain predistortion (DPD) combat intrinsic non-linearity LC-type digitally controlled oscillator (DCO), thus avoiding complications frequency-dependent calibrations. The prototype, implemented in 40-nm CMOS, modulates carrier range 2.7–3.9 GHz 40-MHz reference. measured $-$ 47 dB for 60-Mb/s 64-PSK modulation under case output frequency-divided by notation="LaTeX">$K=8$ , i.e., when DCO exhibits most significant due large fractional FM bandwidth. When or 4, remains below 43 across carrier-frequency tuning and without re-calibrating non-linearity.